Re: gEDA: Icarus Verilog: Is it bug??

[DP Narendra <ndevtapr-at-NOSPAMengineering_dot_uiowa_dot_edu>]

I have one more doubt regarding x propogation and am not sure if Icarus 
does it right?
Take the case -

wire a,b,c,d;
assign a = 1'bx;
assign b = 1'bx;
assign c = 1'b0;
assign d = 1'b1;

wire e = {a,b} == {c,d};

Here, e is assigned 0 but i think it should get x. Am I right.

However 
wire e = ~((a^c) | (b^d));
here e gets x value.


On Wednesday 09 April 2003 01:10 pm, Stephen Williams wrote:
>      this <= #1 (reset) ? 0 : that;
>      foo  <= #1 (reset) ? 0 : bar;
>
> frustum@pacbell.net said:
> > if reset is 'bx, then this and foo will both get set to 'x.
>
> Not quite. If that is 0, then this will get 0, no matter what
> reset is. Same for bar and foo.

-- 
A continuing flow of paper is sufficient to continue the flow of paper.
		-- Dyer

module bug;

wire a, b, c, d;

assign c = 1'bx;
assign a = 1'b1;
assign b = 1'b0;
assign d = 1'bx;

wire e = {c,d} == {a,b};
wire f = ~((c^a) | (d^b));

initial
  begin
    #2
    if ((e == 1'b1) || (e == 1'b0)) 
        $display("FAILED\n");
    else 
        $display("PASSED\n");

    $display(e);
    $display(f);
    $finish;
  end

endmodule