Re: gEDA: What switch level simulator to use?

[Bill Cox <bill-at-NOSPAMviasic_dot_com>]

Hi, Steve and Al.

I looked into gnucap.  It looks like it would be pretty hard to make it
do > 1M transistors.  It looks like a nice tool otherwise.

Irsim sounds more promising, though I agree that starsim/nanosim are the
way to go.  We're still being treated with some hostility from some of
the big EDA players, and it's been hard for us to get copies of tools at
realistic prices.  Mentor has been good, but do they sell any tools in
the starsim/nanosim category?

Without having parasitics properly extracted, I'm not sure it makes
sense for me to do timing-driven simulations.  I have to write a SPICE
reader anyway, and I can do a simple switch-level simulation with a
simple fifo event queue if I don't worry about timing.  It might be
simpler and faster than getting irsim to work for me.  The engine itself
is trivial.  I once wrote one on my HP calculator.

A decision I have  to make right away is weather to write the spice
reader as part of gnetman, or integrate it directly into ViASIC's
proprietary ViaPath tools.

The performance of the ViaPath database is much better, since we
abandoned C style pointers years ago.  Direct integration also would
allow ViASIC customers to skip the step of running gnetman as a
SPICE-to-Verilog translator.  The gnetman database is good, but in
64-bit mode (which these simulations could easily require), we'll need
about 80% more memory and we'll run about 20% slower.  I could go ahead
and build it in the gnetman database, and upgrade the CASE tools to
support efficient 64-bit computing later.  However, if no one but ViASIC
is going to use this capability, I might as well integrate it directly
into ViaPath.

What do you think?

Bill

On Sun, 2004-07-11 at 21:21, Steve Tell wrote:
> On Fri, 9 Jul 2004, Bill Cox wrote:
> 
> > Is there a good super-fast switch-level mosfet simulator in open-source
> > land?  There are commercial ones available, but out of my price range.
> 
> Hi Bill!
> 	Back at UNC we used irsim for some chips that were pretty big at 
> the time (1995-1996), some with >1M devices.   It was possible to load the 
> whole chip and run a small set of vectors, but we mostly subsetted the 
> chip various ways to get the run-time down for most things.
> 
> We still keep it around, but don't do big chips any more.  Starsim/nanosim 
> accelerated spices are the way we seem to be drifting.
> 
> 	 
> > Thanks,
> > Bill
> > 
> > P.S.  If there's not, I'm willing to write one and put it out there in
> > GNU land.  Would there be any interest?  I currently have the SoC
> > Builder project to do, but this project could share some code.
>  
> My impression is that the core algorithm in irsim is still sound.
> At one time I was pretty sure that it was the same one used in 
> some switch-level-mosfet verilog extension from cadence.
> 
> The surrounding code works but could use some updating.
> A few random things that come to mind:
> 
>  - uses a wierd netlist format (although magic can write it).  
> would be nice to read spice or cdl netlist directly.  easy 
> if restriction to flat netlists (no .subckt) is kept.
> 
>  - wierd and crude command language.  We tamed this with wrappers that
> provided a vector-oriented abstraction for input and output.
> 
>  - no true waveform output-file format, and the "analyzer" gui is very
> crufty (X with crude homebrew toolkit - yech). 
>  Ought to be possible to add VCD output, I think.
> 
> 
> I'm in california through friday. 
> interested in lunch sometime after I get home?
> 
> Steve
>