THIS IS NOT A BUG!
Can I say it more strongly?
THIS IS NOT A BUG!!!!!
The test contains a race. A Verilog simulator which conforms to the standard may execute race conditions in any order it chooses. It should tell you something that ncverilog executes this in a different order than Verilog-XL, and ncverilog is newer and faster than Verilog-XL. It should also tell you something that VCS executes this in a different order than Verilog-XL, and coincidentally the same order as ncverilog. It's also newer and faster.
The Cadence AEs my not be aware of the issues, but the developers certainly are, and you will just waste a lot of people's time. I personally spent a lot of time and effort on the IEEE 1364 committee making sure that the behavior of a simulator in the face of a race condition was NOT specified, in order to preserve the flexibility of the simulator writer to implement correct semantics in the most efficient way he could.
Again, BOTH Verilog-XL AND ncverilog (AND VCS AND Icarus AND Modelsim) ARE EXECUTING THIS MODEL CORRECTLY.
John
On Jun 28, 2005, at 7:01 PM, Stephen Williams wrote: -----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1 Stephen Brickles wrote:
|>>XL is, theoretically, that reference, although that's for IEEE1364-1995
|>>and not the -2001 standard. That said, XL seems to be alone on the
|>>particular scheduling issue that these tests bring up, and at this
|>>point I doubt even Cadence cares.
|
|
| Steve,
|
| I am terribly tempted to file this with Cadence as a bug - in that their
| two verilog simulators don't agree on these two files - just to see what their
| AE's say !! Would you have any objection to me sending these two files
| to Cadence as test cases ? Heh! By all means go for it. I'd be curious to hear what comes
of it. Could be fun;-) - --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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