Re: gEDA: Need help resolving a scheduling contradiction

[Anthony J Bybell <netracurse-at-NOSPAMnc_dot_rr_dot_com>]

On Wed, 29 Jun 2005 geda@grfx.com wrote:

> There is (IMO) a slight problem with the view that it's OK to treat
> a continous assign the same way as a gate: while it makes sense for
> the case of "wire x = y & z", the degenerate case of "wire x = w" is
> perfectly realizable in hardware as a short-circuit and as such it
> shouldn't incur ANY scheduling delay (and thereby race conditions).

If wires in Verilog are unidirectional, they function more like buf gates,
not short circuits.  Force x in the PLI and w will keep its old value.

-t