RE: gEDA: Verilogrelative include path handling

["John McCaskill" <jhmccaskill-at-NOSPAMfastertechnology_dot_com>]

> -----Original Message-----
> From: owner-geda-dev@seul.org [mailto:owner-geda-dev@seul.org] On
Behalf
> Of Larry Doolittle
> Sent: Friday, February 03, 2006 4:20 PM
> To: geda-dev@seul.org
> Subject: Re: gEDA: Verilogrelative include path handling
> 
> On Fri, Feb 03, 2006 at 04:19:52PM -0600, John McCaskill wrote:
> > Do you have a road map of the features you will be adding to Icarus
> > posted somewhere? We have started using more advanced features such
as
> > generate,
> 
> generate ... Generate ... GENERATE !!!!
> 

Is this good or bad excitement?  I use Xilinx synthesis tools for FPGA
design.  They added generate since I started using their tools.  I held
off on using generate for a while to maximize how much code I could
simulate with Icarus.  Now I am using it frequently, and it is very nice
to have. 

> > SmartModels for Xilinx PPC and MGTs,
> 
> What are those?

SmartModels are fast behavioral simulation models. For more information
see: 

http://www.synopsys.com/products/lm/swmodel_ds.html

I remember Steve mentioning that he was looking into them a while back.
Xilinx supplies SmartModels to allow you to simulate the embedded
PowerPCs in their FPGAs, and also to simulate the Multi-Gigabit
Transceivers (AKA SERDES blocks) in the FPGAs.  

We use both the PowerPCs and the MGTs in our designs, so I have to have
access to a simulator that supports them.

> 
> > and mixed Verilog and VHDL.
> 
> Ain't gonna happen.  Convert your VHDL to Verilog with vhd2vl,
> then you can mix the designs.  The VHDL synthesis subset where
> that toolchain works OK is broad enough that at least one person
> has learned to stay within it for real designs.
> 
>       - Larry

I have downloaded vhd2vl, but have not tried it yet. We write in
Verilog, so for developing the bits and pieces we only need a verilog
simulator. VHDL comes into play when we are using outside code in full
chip simulations. At that point, we need ModelSim for the SmartModels
anyway.

On a related topic, does anyone know of any code simplification tools
that can read in Verilog, and write out a simpler version. For example,
let it bind some parameters and unroll the generate statements?

Regards,

John McCaskill