Re: gEDA: Icarus verilog synthesis issue

[Erik de Castro Lopo <mle+geda-at-NOSPAMmega-nerd_dot_com>]

David Howland wrote:

> I was hoping someone with knowledge of Icarus could help me out here.
> 
> consider this simple circuit:
> -----------------------------------------------------
> module simple(out, a, b, clk);
> input clk;
> input [7:0] a, b;
> output [7:0] out;
> reg [7:0] out;
> always @(posedge clk) begin
> 	out <= (a & b);
> end
> endmodule
> -----------------------------------------------------
> 
> why would such a simple circuit fail with this error?

What version are you running (iverilog -v)? The above works for me in
this one:

    Icarus Verilog version 0.8 ($Name: v0_8 $)

which is the standard package in Ubuntu Breezy.

Erik
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  Erik de Castro Lopo
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