Re: gEDA: Icarus verilog synthesis issue

[David Howland <dhowland-at-NOSPAMecs_dot_umass_dot_edu>]

I am using iverilog version 0.8.

What command line are you using?  I forgot to mention that I am using a 
slightly hacked version of Icarus (custom output module) and because of 
this I am not using the "iverilog" wrapper binary.    I'm using the 
"ivl" binary directly.

-d

Erik de Castro Lopo wrote:
> David Howland wrote:
> 
> 
>>I was hoping someone with knowledge of Icarus could help me out here.
>>
>>consider this simple circuit:
>>-----------------------------------------------------
>>module simple(out, a, b, clk);
>>input clk;
>>input [7:0] a, b;
>>output [7:0] out;
>>reg [7:0] out;
>>always @(posedge clk) begin
>>	out <= (a & b);
>>end
>>endmodule
>>-----------------------------------------------------
>>
>>why would such a simple circuit fail with this error?
> 
> 
> What version are you running (iverilog -v)? The above works for me in
> this one:
> 
>     Icarus Verilog version 0.8 ($Name: v0_8 $)
> 
> which is the standard package in Ubuntu Breezy.
> 
> Erik