gEDA-dev: gEDA: Iverilog : problem with real number

[Steven Kwan <steven_dot_kwan-at-NOSPAMspeed-pixel_dot_com>]

Hi Steve and all,


Just installed snapshot 20060618 and 
tried to compile pll_model.v (attached).

Problem on line 63.

/////////////////////////////////////////

assign #(6*vcoClkHalfPeriod) resetDoneDelayed = resetDone; // line62 :
compile pass
assign #(6.0*vcoClkHalfPeriod) resetDoneDelayed = resetDone; // line63 :
compile fail
assign #(test) resetDoneDelayed = resetDone; // line64 : compile pass

/////////////////////////////////////////



[kk@spl2]$ iverilog -tnull pll_model.v
pll_model.v:63: error: Real constants are not synthesizable.
sh: line 1:  3417
Done                    /eda/iverilog-20060618/lib/ivl/ivlpp -L
-D__ICARUS__=1 -f/tmp/ivrlg2c4caf8c
      3418 Segmentation fault      | /eda/iverilog-20060618/lib/ivl/ivl
-C/tmp/ivrlh2c4caf8c -C/eda/iverilog-20060618/lib/ivl/null.conf -- -



[kk@spl2]$ iverilog -V
Icarus Verilog version 0.9.devel ($Name: s20060618 $)

/////////////////////////////////////////



Thank you for your support.

Best regards,
Steven.

///
/// File    : pll_model.v
/// NOTE    : this is cropped from pll.v and for testing iverilog only, 
///           not a real model
/// owner   : Steven Kwan
/// date    : 20060505
///


`timescale 1ns/1ps      
`define SETTLINGTIME 42000

`define DIVCLKNOM 2.000000e-3
`define VCOCLKNOM 100.000000e-3

`define DIVCLKTOL 0.300000
`define VCOCLKTOL 0.250000

`define KVCOTYP 393.600000

module pll ( divClkin, 
	     FBD,
	     vcoClk, 
	     filterVoltageBus);

input divClkin;        
input [7:0] FBD;

output vcoClk;
output [63:0] filterVoltageBus;

reg resetDone; 

wire resetDoneDelayed;  
reg  vcoClk;

real divClkPeriod; 
real vcoClkHalfPeriod;
real test;

wire [63:0] filterVoltageBus = $realtobits(filterVoltage);


initial 
   begin
   divClkPeriod = 1/`DIVCLKNOM;          
   resetDone = 0;
   vcoClkHalfPeriod = 0;
   vcoClk = 0;
   end

always @ (posedge divClkin) 
   begin 
   vcoClkHalfPeriod = divClkPeriod/((FBD+1)*2.0);
   end

always @ (vcoClkHalfPeriod) 
   begin 
   test = 6.0*vcoClkHalfPeriod; // for testing line63 
   end

assign #(6*vcoClkHalfPeriod) resetDoneDelayed = resetDone; // line62 : compile pass
assign #(6.0*vcoClkHalfPeriod) resetDoneDelayed = resetDone; // line63 : compile fail
assign #(test) resetDoneDelayed = resetDone; // line64 : compile pass


endmodule 

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