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Re: gEDA-dev: Blind and buried vias in PCB... who is doing what?

I always thought chasing down which vias thermals were shorting out a
net to be similar to a game of Where's Waldo.

Steve Meier

Levente wrote:
>On Tue, 18 Jul 2006 04:10:40 -0700
>ldoolitt@recycle.lbl.gov wrote:
>
>  
>>I would also like to remind people in this context that there
>>is a request for four states of joining (or not) of a via to
>>the polygon (if any) per layer:
>>  0: no connect
>>  1: traditional X thermal
>>  2: alternate + thermal
>>  3: solid connection
>>    
>
>I think there should be a 5th, which is "auto", when the logic would select trace(s) from x and +, that does not short anything.
>
>Levente
>
>--
>http://web.interware.hu/lekovacs
>  
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