Re: gEDA-dev: Numerical analysis of circuit boards

[Dan McMahill <dan-at-NOSPAMmcmahill_dot_net>]

Tomaz Solc wrote:
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> Hi
> 
> 
>>What techniques are you using? Also, how do you validate your results?
> 
> 
> I'm using a finite difference method.
> 
> So far I have only validated the results by trying some simple
> geometries and comparing the values returned by my software with those
> that can be analytically calculated. I'm also planning to make some
> printed circuit boards with test patterns and compare the calculated
> values with measurements.
> 

Have you read any papers (I suspect they exist, but I haven't looked) 
about how tools like cadences's assura tool do capacitance extraction 
for IC layout?  Also I've heard that magic also has a capacitance 
extractor.  Assura does its work by running something like fastcap over 
a whole bunch of structures and it builds up a table.  Then it does some 
sort of fast calculation on the actual layout using the table  and some 
sort of interpolation.  It is done this way in an attempt to combine a 
field solver for some accuracy with an algorithm which is fast enough to 
be practical for a real layout.


> I'm currently loading the copper geometry from PNG files. I take a board
> drawn in PCB, export it to postscript and convert postscript to PNG
> images. Pin locations still must be entered by hand.
> 

PCB can export directly to png.

-Dan


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