Re: gEDA-dev: about gEDA hierarchical netlist

[Mike Jarabek <mjarabek-at-NOSPAMistop_dot_com>]

Hi,

On Sat, 2006-09-23 at 06:56 -0400, pt75234@aim.com wrote:
> Hi Everyone,
> I am new to this posting. I've been trying to find out more about 
> hierarchical Verilog/VHDL/Spice netlist features in gEDA. I searched 
> and found some discussions on this topic from the geda-dev May 2006 
> maillist archive regarding spice's hierarchical netlist. I had also 
> tried to actually run some test examples to understand the hierarchical 
> netlist feature in gEDA in general. Similar to what others had said in 
> the May 2006 maillist, my test run only got flatten hierarchical 
> netlist from gEDA netlisters. So I decided to experiment and wrote a 
> crude bash script to generate a non-flatten hierarchical verilog 
> netlist first as a proof of concept. The script is quite simple, it 
> gathers hierarchical info from sch and sym files of each hierarchy 
> levels in the design, generate a unique sym/sch list and invoke gEDA's 
> gnetlist verilog to do each level of netlisting. As each level is 
> processed, netlists of all hierarchical levels from different unique 
> modules are concatinated into one netlist file. The script also 
> generates a report file for the entire hierarchy of the design.
> 

I usually use a makefile that knows how to convert schematics to
verilog/vhdl with a rule. I don't usually put the source file attribute
on my symbols so that the netlister does not recurse into the lower
levels, and generate a flat netlist.

Once I have the separate HDL files I use the project file or manifest
file features of the simulator or synthesis tool to link them all
together.  No need to generate a giant monolithic source code file.
This also gets you incremental compilation if your simulator supports
it. (Modelsim can work this way.)



> If you are interested, I'll be glad to post the script up. Ah, I have 
> yet to learn the rule of posting files here; whether I should email it 
> as an attached file, or I have to upload it elsewhere? Or is there a 
> HOW-To that I can read to find out?
> 
> Best regards,
> Paul Tan
> 
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-- 
--------------------------------------------------
                              Mike Jarabek        
                                FPGA/ASIC Designer
  http://www.istop.com/~mjarabek                    
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