gEDA-dev: iverilog: problems with constant expr in conditional

[Evan Lavelle <sa212+geda-at-NOSPAMcyconix_dot_com>]

Icarus 0.8.3 seems to have problems with a literal expression in a 
conditional statement:

module test;
   initial
     main;
   task main;
     begin
       if(2)
         $write("taken 'if' branch\n");
       else
         $write("taken 'else' branch\n");
     end
   endtask
endmodule

This (machine-generated) code takes the else branch, and not the if 
branch. iverilog seems to be checking just the bottom bit of the 
conditional; 'if(3)' works Ok.

This code segfaults on compilation:

module test;
    initial
      main;
    task main;
       begin
	 if(1)
	   ;
       end
    endtask
endmodule

--
Evan


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