Re: gEDA-dev: Diode symbols in GSchem and PCB

[John Doty <jpd-at-NOSPAMwispertel_dot_net>]

On Dec 15, 2006, at 11:30 AM, DJ Delorie wrote:

>
> My thought is to do something like this (indenting added for
> readability), assuming we have some sort of mapping from symbol to
> footprint (which I noted before, which maps the symbolic pin names to
> physical pin numbers for a given package/variant (like dual or quad op
> amp, sot23 vs dip 8, etc)).
>
> Here's a typical component instantiated in a .sch file:
>
> C 69700 50400 1 0 0 resistor-1.sym
> {
>   T 69950 50700 5 10 1 1 0 0 1
>   refdes=R102
>   T 70000 50200 5 10 1 1 0 0 1
>   value=100
> }
>
> Now here's a typical pin instantiated in a .sym file:
>
> P 3300 1600 3600 1600 1 0 1
> {
>   T 2700 1600 9 10 1 1 0 0 1
>   pinlabel=C
> }
>
>
> In the proposed scheme, one could overwrite the .sym pin by having the
> following component in the .sch file:
>
> C 69700 50400 1 0 0 resistor-1.sym
> {
>   T 69950 50700 5 10 1 1 0 0 1
>   refdes=R102
>   T 70000 50200 5 10 1 1 0 0 1
>   value=100
>   P "C"
>   {
>     T 3400 1650 5 8 1 1 0 0 1
>     pinnumber=15
>   }
> }
>
> Note that we don't try to number the pins in the symbol, and we use
> the label to identify the pins (not the location).
>
> DRC would then complain about symbols without pin numbers, which would
> now mean that you haven't yet mapped the symbols to a package/variant,
> rather than just a bug in the symbol.
>
> It does mean that labels must be unique, but that should be OK, as
> long as we can map one pin label to more than one pin number (such as
> for power pins).
>
> Alternately, we could have pinnumbers in the symbol yet still allow
> the .sch to override them, but we'd still use the pin label to
> identify which pin.
>
> The neat part of this is that we can support complex slotting without
> using any of the slotting attributes, just by re-overriding the pin
> numbers themselves.  The slotting info would still need to be stored
> somewhere, of course.  Example: a triple 3-in NAND should allow for
> (1) selecting which of the three gates, and (2) rearranging the input
> pins for each gate.  Likewise, for SRAM, it would be nice to be able
> to "sanely" rearrange the various data pins.

The problem is that there is no attribute you can use as a pin  
identifier:

You might want to change "pinlabel", particularly in an FPGA where  
you'd like to replace a generic label with an application-specific  
one. "pinlabel" also isn't always unique, some parts have several  
"NC" pins or have multiple pins connected to the same internal node.  
"pintype" generally isn't unique. "pinnumber" varies depending on  
package. The best might be "pinseq", but while there are some defacto  
standards here, a particular SPICE model may force you to change the  
sequence, or the symbol creator may not have understood the purpose  
of "pinseq". Net topology is already fundamentally geometrical in  
gschem, go with it, don't fight it. PCB is a different game...

John Doty              Noqsi Aerospace, Ltd.
jpd@noqsi.com




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