gEDA-dev: Icarus: Strange problem with Z's being turned into zerosin output wire vector.

["Timothy Miller" <theosib-at-NOSPAMgmail_dot_com>]

Hi, everyone.

I hope I'm not posting to the wrong mailing list.  Someone on OGML had
suggested that I join this list for discussing issues with Icarus.
I'm using Icarus to simulate designs for the Open Graphics Project,
and I've run into a snag that I hope I could get some advice on.  I've
got a bug in my design that's holding me up, and I can't debug it
until I can get the simulation to work correctly.  BTW, I'm using the
absolute latest Icarus from CVS.

The trouble I'm having has to do with the two modules I've included
below.  They're for building up tristate busses on an FPGA.  They
synthesize to the right thing with ISE Foundation, and they simulate
correctly under ModelSim.  With Icarus, I'm having Z's get wiped out
and come out as zeros instead.

The simulation I'm running is of a very large design, and in there I
have an instance of ddrff4.  The Q output of the ddrff1 submodule is Z
when OE is deasserted, and I can
see that Q0 though Q3 are also the correct values.  If I do this:

assign Q = {Q3, Q2, Q1, Q0};

the bits in Q lose the Z's, and the Z's come out as zeros.  That is,
Q0 through Q3 are okay, but Q[0] through Q[3] are wrong.

If I do this:

assign {W3, W2, W1, W0} = {Q3, Q2, Q1, Q0};
wire [3:0] W = {Q3, Q2, Q1, Q0};

Then all of W0 through W3 and W[0] through W[3] are correct.  But if I
then decide run the simulation again with this change:

assign Q = W;

Then not only is Q wrong, but so is the W.  It's like whatever is
wrong with the output Q infects W if you assign W to Q.

The really strange thing is that when I isolate the modules into a
small, they work just fine.  Identical code, different environment,
different behavior.  This means I can't produce a simple test case.
Any suggestions on how I might track down the problem?


Thanks in advance for your help!


module ddrff1(Q, C0, C1, D0, D1, OE);
input C0, C1, D0, D1, OE;
output Q;
wire R;
FDDRRSE ff0  (.Q(R), .C0(C0), .C1(C1), .CE(1'b1), .D0(D0), .D1(D1),
.R(1'b0), .S(1'b0));
assign Q = OE ? R : 1'bz;
endmodule

module ddrff4(Q, C0, C1, D0, D1, OE);
input C0, C1, OE;
input [3:0] D0, D1;
output [3:0] Q;
wire Q0, Q1, Q2, Q3;
wire W0, W1, W2, W3;
//assign Q = {Q3, Q2, Q1, Q0};
assign {W3, W2, W1, W0} = {Q3, Q2, Q1, Q0};
wire [3:0] W = {Q3, Q2, Q1, Q0};
assign Q = W;
initial begin
   $monitor("Qs %d, %d, %d, %d", Q3, Q2, Q1, Q0);
end
//ddrff1 ff0  (.Q(Q[0]), .C0(C0), .C1(C1), .D0(D0[0]), .D1(D1[0]), .OE(OE));
//ddrff1 ff1  (.Q(Q[1]), .C0(C0), .C1(C1), .D0(D0[1]), .D1(D1[1]), .OE(OE));
//ddrff1 ff2  (.Q(Q[2]), .C0(C0), .C1(C1), .D0(D0[2]), .D1(D1[2]), .OE(OE));
//ddrff1 ff3  (.Q(Q[3]), .C0(C0), .C1(C1), .D0(D0[3]), .D1(D1[3]), .OE(OE));
ddrff1 ff0  (.Q(Q0), .C0(C0), .C1(C1), .D0(D0[0]), .D1(D1[0]), .OE(OE));
ddrff1 ff1  (.Q(Q1), .C0(C0), .C1(C1), .D0(D0[1]), .D1(D1[1]), .OE(OE));
ddrff1 ff2  (.Q(Q2), .C0(C0), .C1(C1), .D0(D0[2]), .D1(D1[2]), .OE(OE));
ddrff1 ff3  (.Q(Q3), .C0(C0), .C1(C1), .D0(D0[3]), .D1(D1[3]), .OE(OE));
endmodule


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