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Re: gEDA-dev: Need a Verilog test run
Output from Verilog XL...
Tool: VERILOG-XL 05.70.001-p Jan 19, 2007 11:15:19
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Compiling source file "test.v"
Highest level modules:
test
At 1 value is 0000000000
At 2 value is 00000xxxxx
At 3 value is 1111111111
At 4 value is 00000xxxxx
At 5 value is 0000000000
At 6 value is 00xxxxxxxx
L13 "test.v": $finish at simulation time 7
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool: VERILOG-XL 05.70.001-p Jan 19, 2007 11:15:21
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