Re: gEDA-dev: Need a Verilog test run

[Stephen Brickles using shaun <stephen-at-NOSPAMmlp_dot_intersil_dot_com>]

Output from VCS:

*** Using loader /usr/ccs/bin/ld instead of cc ...
                         Chronologic VCS (TM)
            Version Y-2006.06 -- Fri Jan 19 11:22:41 2007
               Copyright (c) 1991-2006 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'test.v'
Top Level Modules:
       test
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
../simv up to date
CPU time: 0 seconds to compile + 1 seconds to link

Chronologic VCS simulator copyright 1991-2005
Contains Synopsys proprietary information.
Compiler version Y-2006.06; Runtime version Y-2006.06;  Jan 19 11:23 2007

At 1 value is 0000000000
At 2 value is 00000xxxxx
At 3 value is 1111111111
At 4 value is 00000xxxxx
At 5 value is 0000000000
At 6 value is 00xxxxxxxx
$finish at simulation time                    7
           V C S   S i m u l a t i o n   R e p o r t 
Time: 7
CPU Time:      0.270 seconds;       Data structure size:   0.0Mb
Fri Jan 19 11:23:06 2007



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