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gEDA-dev: verilog operator precedence question: logical & andreduction |
Hello Stephen,
Here is another contruct that our compiler barfs on:
input Tclk;
output out;
reg [35:0] Vsel;
reg [35:0] bits;
assign out = |(bits & Vsel) & Tclk;
and in this case it may have a point.
In Lee: Verilog Quickstart, 2nd Edition, page 80, the operator
precedence table does not list the reduction operators seperately.
That could be read that the bitwise & has higher precedence than
the reduction |. Iverilog treats the reduction operator with higher
precedence than the bitwise operator.
OTOH, writing it in the reverse order should be unambiguous:
assign out = Tclk & |(bits & Vsel);
What do the relevant standards have to say about this?
Cheers
Stephan
module test;
reg [7:0] a;
reg [7:0] m;
reg p;
wire o = |(a&m) & p;
always
begin
#1 p <= 1;
#1 $display("%b %b %b %b", a,m,p,o);
#1 p <= 0;
#1 $display("%b %b %b %b", a,m,p,o);
a <= a+a;
end
initial
begin
p <= 0;
m <= 8'b 11010110;
a <= 8'b 00000001;
#33 $finish();
end
endmodule // test
Stephen Williams <steve@icarus.com> writes:
> Stephan Boettcher wrote:
>> Hi Steve,
>>
>> The following code runs fine on iveriog, but some synthesizers
>> complain about it:
>>
>> wire next;
>> reg [1:0] worda;
>> wire read = next | |worda;
>>
>> Is there an issue with the relevant standards, with some opportunity
>> for a warning by ivl?
>
> There is no ambiguity. || is one token, and | | are two tokens.
> I see no way that a reasonable parser would be able to confuse
> this with logical or (||). The point of the warning might be to
> catch typos, though.
>
>> Cheers
>> Stephan
>>
>>> reg [1:0] worda;
>>> wire read = next | (|worda); // 6-22, JC
>>>
>>> // Compile ERROR: Reduction OR follows bitwise OR operator, consider using brackets to disambiguate.
>>> // wire read = next | |worda; // 6-22, JC
--
Stephan Böttcher FAX: +49-431-880-3968
Extraterrestrische Physik Tel: +49-431-880-2508
I.f.Exp.u.Angew.Physik mailto:boettcher@physik.uni-kiel.de
Leibnizstr. 11, 24118 Kiel, Germany
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