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gEDA-dev: Icarus Verilog, problem with output from $display?



It could be that I'm simply biased by what these mean in C, but, I'm
getting the same output from these two statements, and I don't expect
to:

$display("%06x", mywire);
$display("%6x", mywire);

If mywire==4, for the first one, I expect to see "000004", instead,
I'm seeing "     4".

Is there no way to get zero-padded output?  Or is this a bug in icarus?

-- 
Timothy Miller
http://www.cse.ohio-state.edu/~millerti


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