gEDA-dev: Re: Icarus Verilog, problem with output from $display?

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Timothy Miller wrote:
> It could be that I'm simply biased by what these mean in C, but, I'm
> getting the same output from these two statements, and I don't expect
> to:
> 
> $display("%06x", mywire);
> $display("%6x", mywire);
> 
> If mywire==4, for the first one, I expect to see "000004", instead,
> I'm seeing "     4".
> 
> Is there no way to get zero-padded output?  Or is this a bug in icarus?
> 

A little of both. Standard verilog does not allow you to specify
the width at all. It will always print out in a size given by the
width of the item being printed. The exception is that you can put
a "0" between the '%' and the 'h' to force it to print the minimum
size for the value. (By the way, you meant 'h' not 'x'. Icarus Verilog
accepts the 'x' as an extension.)

Icarus Verilog is more generous in that it adds an an extension
support for explicit widths a la C formats.

The bug here is that binary, hex and octal values should be zero
padded always, and decimal values not zero-padded. Also, I see in
the code that I tried to do something useful with leading zeros
in the field size, but your results suggest I missed.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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