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gEDA-dev: Icarus Verilog and Xilinx unisim files
Dear Stephen,
thanks for the fixes for my recent reports. Now I want to run the top level
of my design that instantiates a block ram. This hits another assertion.
>iverilog -o /tmp/a.out RAMB16_S9_S36.v ../glbl.v
ivl: eval_expr.c:1660: draw_select_signal: Assertion `0' failed.
sh: line 1: 32620 Done /usr/local/lib/ivl/ivlpp -L -F/tmp/ivrlg2e76bb53 -f/tmp/ivrlge76bb53
32621 Abgebrochen | /usr/local/lib/ivl/ivl
-C/tmp/ivrlhe76bb53 -C/usr/local/lib/ivl/vvp.conf -- -
Are you interested in those kind of reports too? Should they be checked into
the bug database?
You can get access to the Xilinx unisim file by downloading Xilinx ISE
Webpack for free. I guess however, you already have access to ISE.
B.t.w, is there a way to run iverilog in the debugger? A backtrace at the
point where the assertion is hit might help to fix (or work around) bugs
myself.
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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