gEDA-dev: Re: VHDL, was Re: Hierarchical buses

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

al davis wrote:

> I proposed inheritance (as in C++) to the Verilog-AMS committee, 
> but it was not accepted.  I had a complete proposal with syntax 
> and semantics.  This would have been more capable than VHDL's 
> entity/architecture, and simpler, and fully compatible with old 
> Verilog.  They did include a watered down variant 
> as "paramset", that lost the original reason for the proposal.  
> It added the functionality of the spice ".model" card.

Is it written up? Make sure I have a copy so that when I get
around to AMS extensions I can look at it. I'm not above (or
beneath) adding extensions to the language.




-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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