Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

On Wednesday 21 March 2007 16:44, Stephen Williams wrote:
> al davis wrote:
> > On Wednesday 21 March 2007 15:38, Stephen Williams wrote:
> >> There is also, dare I say it, EDIF. The big vendors may
> >> have botched their use of EDIF, but it does have the
> >> advantage that it reflects netlist, and also other
> >> information like schematics information.
> >>
> >> It is also easier to parse. VHDL is simple on the surface
> >> but a VHDL parser gets very complicated very quickly.
> >
> > EDIF has a Lisp like syntax.  contrast .. VHDL has a ADA
> > like syntax, Verilog claims to have a C like syntax, but
> > botched it. It's more like PL-I, and somewhat inconsistent.
>
> You can find juicy insults for every format, I'm sure. (I can
> offer some choice words for all those bl*dy parenthesis.)
> That's not the point.

I prefer the Verilog syntax over the others.  When you have 
design by committee these things happen.

>
> > So, yes, EDIF is easier to parse.  Parsing is a tiny piece
> > of the whole problem.
>
> Granted.
>
> > How do you do the entity/architecture concept with multiple
> > architectures?
>
> You would use "view"s. The view types include graphical,
> netlist, behavioral, schematic, and a few others. The EDIF
> format was designed to carry a design from abstract
> description down through schematics and netlists to layout.
>
> > How about behavioral modeling?  Remember ..  this is for an
> > interchange format, hopefully no more than one step away
> > from lots of native formats.  Behavior is one of them.  
> > Can you make a lossless transformation from Verilog to EDIF
> > and back?
>
> See above. But I have views on the concept of translating
> general Verilog/VHDL in, out and across. I believe that
> constrained subsets can certainly be handled though.
>
> > What applications use it as native?  I am not aware of any
> > analog/mixed-signal simulators that use EDIF as the native
> > language.
>
> I don't know about native, but I know that Xilinx tools can
> import EDIF netlists, and there are a variety of commercial
> schematic tools that claim support for EDIF schematics, at
> least for import/export. Anything that can read an EDIF
> netlist and the attributes should be able to get enough
> information to simulate.

That's digital.  I am thinking analog, digital, mixed-signal, 
etc.   I am not aware of any big pressure to use EDIF for 
analog.
>
> > I believe it is possible to make a lossless transformation
> > from full Verilog-AMS to VHDL-AMS and back again. 
> > Remember, for a common interchange format, it must be
> > possible to make a lossless transformation from any native
> > format to the interchange format, and back to the original.
>
> I'm not an expert in EDIF, but it appears that there are
> enough behavioral statements to carry behavioral descriptions
> of cells. (Cells are the edif equivilent of modules or
> entities.) They are somewhat abstract. Later versions of EDIF
> may have added to the set.
>
> As for losslesly transferring back and forth between VHDL and
> Verilog in general, well that's just not reasonable. Their
> schedulers are subtly different, as are their data types.
> Both languages are complete enough that you can theoretically
> write a program in A that exactly matches B, but the result
> will not be reverseable in a way that will get your original
> back. If you have a Verilog description, then it should stay
> Verilog, and vis versa.
>
> Or at least in the digital world. Paradoxically, the analog
> bits may transform much more readily. I'm no expert there.
>
> If you constrain the subset of behaviors you want to
> transport, and define some useful caveats, then that's
> different and yes I believe you can achieve lossless
> back-and-forth translation, and yes I suspect EDIF can be
> included in the mix.


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