Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

On Wednesday 21 March 2007 17:56, Stephen Williams wrote:
> > I proposed inheritance (as in C++) to the Verilog-AMS
> > committee, but it was not accepted.  I had a complete
> > proposal with syntax and semantics.  This would have been
> > more capable than VHDL's entity/architecture, and simpler,
> > and fully compatible with old Verilog.  They did include a
> > watered down variant
> > as "paramset", that lost the original reason for the
> > proposal.   It added the functionality of the spice
> > ".model" card.
>
> Is it written up? Make sure I have a copy so that when I get
> around to AMS extensions I can look at it. I'm not above (or
> beneath) adding extensions to the language.

Yes.  It is in the "AMS-LRM-2-2.pdf" official document, which is 
a free download.

How do you feel about adding inheritance or the 
entity/architecture concept?


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