Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

Yikes .... I hit the wrong button ,, send when I wanted to put 
aside.

On Wednesday 21 March 2007 18:10, al davis wrote:
> On Wednesday 21 March 2007 16:44, Stephen Williams wrote:

> > As for losslesly transferring back and forth between VHDL
> > and Verilog in general, well that's just not reasonable.
> > Their schedulers are subtly different, as are their data
> > types. Both languages are complete enough that you can
> > theoretically write a program in A that exactly matches B,
> > but the result will not be reverseable in a way that will
> > get your original back. If you have a Verilog description,
> > then it should stay Verilog, and vis versa.

Agreed.  What is important here is the structural subset as an 
interchange format, and the realization that the conversion to 
simulation probably means to augment with the information that 
isn't in the schematic, which is often a behavioral model.  
These would probably not be translated.

Therefore, the format spec should allow for behavioral modeling, 
but the translators for schematic, PCB, and the like will 
probably never need to deal with it.  It's just one of those 
architectures for someone else.

> > If you constrain the subset of behaviors you want to
> > transport, and define some useful caveats, then that's
> > different and yes I believe you can achieve lossless
> > back-and-forth translation, and yes I suspect EDIF can be
> > included in the mix.

OK.....  Are you telling me that if there is a choice between 
Verilog and EDIF, that you prefer EDIF?


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