gEDA-dev: Re: VHDL, was Re: Hierarchical buses

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

al davis wrote:

>>> If you constrain the subset of behaviors you want to
>>> transport, and define some useful caveats, then that's
>>> different and yes I believe you can achieve lossless
>>> back-and-forth translation, and yes I suspect EDIF can be
>>> included in the mix.
> 
> OK.....  Are you telling me that if there is a choice between 
> Verilog and EDIF, that you prefer EDIF?

If you are only interested in carrying netlist data, then I
personally prefer Verilog. But if you want to include schematic
information, layout information, want to communicate back and
forth between gschem, pcb, gnucap, and others, then I think
EDIF would be better because the drawing stuff is available as
part of the standard (allowing one to go *back* to the schematic
after processing elsewhere) whereas with Verilog or VHDL, schematic
details would have to be bolted on.

If I correctly grasp what you are trying to do, then I think that
EDIF as an interchange format is the way to go. It covers the most
bases right off the bat, and is most easily extended for the few
bases that remain.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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