Re: Hidden Nets Re: gEDA-dev: New diagram (attempt at UML)

[Peter Clifton <pcjc2-at-NOSPAMcam_dot_ac_dot_uk>]

On Thu, 2007-03-22 at 09:21 -0800, Steve Meier wrote:
> This subject has come up a few times.
> 
> Traditionaly gaf has allowed symbols to have net attributes. Common ones
> are net=VCC or net=gnd. These attributes are typically not visible,
> which is why I call them hidden.

Those do present difficulties. In general, I think they are a bad idea,
but its not like we can just ignore the stuff which uses them.

It might be possible to re-expose them as Mports which can be
automatically wired up to identically named nets at the next level down.

[snip]

> In my code, I allow the hidden net attribute. But if the device has one
> of the pins in the hidden net as also a graphical pin then rather then
> associating that hidden net with a schematic level net I make that
> hidden net become connected to whatever net is connected to the
> graphical pin.

If I understand you correctly, this is almost like I suggested above,
but allows user-defined re-mangling of the net name. You're explicitly
giving a graphical pin (with a different net name) to replace, say
"VCC".

Sounds good. Would work with the above case, and for symbols with fully
hidden nets, we can just expose an Mport, and auto-magically look to
connect it to a net named "VCC" one level down.

> A third use was proposed by DJ and I intend to implement it, is for BUS
> pins on symbols (complex) to have a list of pins associated with it.
> Then each pin gets attached to a net from the bus in the order of the
> bus attribute and the order of the pin in the more then likely hiden
> list of pins.
> 
> I stated:
> 
> I don't support the slot concept for buses I am not sure their is
> a need since I expect symbols that have busses are just graphical
> constructs that must have attached schematics
> 
> DJ responded:
> 
> "RAM chips.  My original purpose was to avoid having dozens of pins on
> a symbol, since that bloats the size of the symbol.  The spec sheets
> usually just have a bus line coming out of the chip's symbol."

Absolutely, this is exactly the sort of thing I wanted to see. Of
course, we don't necessarily want to number "pins" as if they are metal
leads on a semiconductor. (Think of the multiple-package problem).

They would be either referred to by signal name "A0" etc.. for an
address bus, or by some allocated number - not necessarily matching any
particular package.

Regards,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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