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Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
On Thursday 22 March 2007 20:05, Justyn Butler wrote:
> I think now I'll submit two proposals for SoC, which gives
> gEDA several weeks to decide which is more crucial for the
> summer. It's pretty frustrating because I'd like to work on
> so many different things.
>
> I'll leave the Gerber converter because it would be
> implemented as a new, external program. I have an ulterior
> motive - I'd like to work on PCB itself in some way because
> it will help (force) me to become very familiar with it's
> inner workings, so I'll be able to continue coding on it in
> the future.
>
> My planned proposals:
> 1) DRC and non-copper layer overhaul.
> 2) gsch2pcb overhaul including component
> updating/replacement.
>
> I'll get to work on the formal proposals, and then I'll
> probably post them here for some feedback if that's OK.
The most valuable one is #2, if you do it with the VHDL
intermediate file I proposed. You can do Gerber too, the same
way. Once you get into it, I think you will see how easy it is
to add importers for foreign formats like Eagle and Orcad, all
in one summer.
It's a new external program, which I think is good for you. You
get something to show, that does something important. It fixes
a gaping hole in the system, a hole that drives many away.
I will help you on the formats and architecture.
If you do this, it also provides files that gnucap can use for
simulation, which is something we don't really have now.
The existing netlister does not work very well. I just tried a
test case, to see the status now ... I made a reasonable
schematic, and tried all 4 relevant netlisters. (vhdl, verilog,
spice, spice-sdb) None gave an output that was directly usable.
All of them were missing critical information that is in the
schematic.
It will be noticed by people who can help you with your career,
and it will be a great learning experience.
Doing the translator, through VHDL, will provide extra
capability well beyond the dreams of most people here.
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