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Re: gEDA-dev: Re: VHDL as a file format



On Wednesday 21 March 2007 06:00, Evan Lavelle wrote:
> Hang on. I haven't been following this thread, but there does
> seem to be some idea that VHDL can be used as a "schematic"
> representation. It can't - it codes point-to-point
> connectivity, but it can't code any spatial or geometric
> information about *how* the connection is drawn (arcs,
> straight lines, unrouted rats nest, routed, whatever). VHDL
> and Verilog don't do this. You have to go to a much lower
> level (GDSII, OASIS, etc) to get this information.

Look at any of those files.  What do you see?

There are blocks ..
In each block, there is a list of objects.
Each object has a name, type, connections, attributes.

That's all!

It doesn't take much of a language to handle this.  

The base language doesn't need to know what the meaning 
of "arc" "rat" "resistor" or whatever.  Either another block 
(architecture, in VHDL) defines what it means, or it is 
implicitly known by the tool.

VHDL and Verilog are both used for non-electrical applications, 
because they are general purpose modeling languages.

You may be confused by "what is a connection".  It is easy to 
think of a node or net name, as in Spice.  It could be a 
physical location, a time, or some other abstract concept.  
It's just a name.

From the simulation view, I need a complete lossless translation 
of whatever is on the board, the schematic, etc.  
Supplying "architectures" for the objects makes it possible to 
simulate it.

I see VHDL and Verilog as the only choices.  They do what we 
need.  A modern simulator can simulate from them, probably 
without further translation.  Other languages or a homemade 
language could represent the blocks and lists of objects, but 
we need to design everything, and it is non-standard.

The only reason for VHDL over Verilog is the entity/architecture 
concept.  We could extend Verilog to do it, but then we would 
be deviating from the official definition of the language.  It 
is a very easy extension.


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