Re: gEDA-dev: Re: VHDL as a file format

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

On Friday 23 March 2007 11:02, Stephen Williams wrote:
> He's not actually proposing to use VHDL but to steal some
> syntax from VHDL and interpret it as he sees fit for the
> task. In particular, he's only interested in the
> entity-architecture separation. In other words, he's defining
> a new set of semantics for (parts of) an existing syntax.

Actually I am proposing VHDL, the structural subset.  It 
describes hardware.  That's all.  What you do with the 
description is up to you.

Verilog would work, too, except for the need for a mechanism for 
having multiple architectures for a single entity.  We could do 
that with a forced naming convention or something like that.


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