Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

On Friday 23 March 2007 13:56, Mike Jarabek wrote:
>   Attaching named attributes to instantiations in the Verilog
> netlister has been on my todo for a long time. I will add
> this.
>
>   I will look more into the special ground node naming, this
> is something I have not seen before. But likely because I
> have never used Verilog-AMS. I don't see any difficulty in
> creating a special symbol to denote this kind of net and
> teaching the backend to handle it. I will investigate.

Thanks ..

By the way .. My proposal is not about any specific tool, but 
rather a concept of a common intermediate format, based on a 
standard hardware description language.  gnetlist can be part 
of it.

The fundamental problem with gnetlist is that it uses the 
schematic, ".sch" file, as a common point.  I want to use 
either Verilog or VHDL as the common point.


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