Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

On Friday 23 March 2007 13:56, Mike Jarabek wrote:
>  I don't see any difficulty in creating a special symbol to
> denote this kind of net and teaching the backend to handle
> it.

I see difficulty with anything special.

In an *AMS language, nets have types.  It's not just "wire". The 
schematic needs to be extended so that pins on symbols can have 
types.  It is not prohibited to mix types.  Verilog has 
something called a "connectmodule" to define how to resolve 
mixed types.

Although gnucap does not yet support the connectmodule syntax, 
it is the first simulator, ever, to have a correct 
implementation of the concept, long before either Verilog-AMS 
or VHDL-AMS existed.

Take a look at the spice netlister to see what I mean.  The 
spice syntax is so irregular that almost everything is special.  
The netlister has special code for lots of specific symbols.  
The only way around that I see is to abandon the spice format, 
which the industry is trying to do.


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