Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS

[Stuart Brorson <sdb-at-NOSPAMcloud9_dot_net>]

Al said
>>  The existing netlister does not work very well.  I just tried a
>>  test case, to see the status now ...  I made a reasonable
>>  schematic, and tried all 4 relevant netlisters. (vhdl, verilog,
>>  spice, spice-sdb) None gave an output that was directly usable.
>>  All of them were missing critical information that is in the
>>  schematic.

> On Friday 23 March 2007 09:34, Stuart Brorson wrote:
>> It would be interesting to see your test schematic.

OK, thanks.  I took a look at it.  It's a single op-amp powered by
two batteries.  It's an inverting amp, gain=1.  You have an AC source
driving the input through a pot.

As you know very well, this is an analog schematic.  Therefore, the
VHDL and the Verilog netlister won't produce any useful output 'cause
they're not designed for this kind of work.

As for the SPICE netlisters, "spice" won't do anything with this since
gEDA's original SPICE netlisters are rather primitive.  "spice-sdb"
could handle this circuit, but you (purposely) did things to make it
fail:

*  SPICE has no concept of a pot, as you know, so that component won't
    appear in the netlist. 
*  SPICE has no concept of a battery, so it won't netlist either.
*  You didn't include any .subckt card for the op amp, so ngspice
    can't do anything with it.
*  There is no analysis defined via a SPICE directive card, so again
    no analysis command will show up in the netlist.
*  Your resistors include an attribute r=10K (or some value) which
    won't netlist in spice-sdb since spice-sdb cues off of the "value"
    attribute to get the resistance.

I assert that this circuit is simulatable using gEDA in its current
form if you just follow the rules.  Therefore it's inaccurate to say:

>>  The existing netlister does not work very well.

since your circuit deliberately does things which are designed
to preclude proper netlisting.  But of course you know all this.

If I am not mistaken, your point is that you can't enter any old
schematic and expect to generate a correct netlist using gnetlist.
But that's also true of any commerical tool out there, so the point is
kind of moot.

Or maybe your point is that gEDA isn't a universal simulation
environment.  That's true, but creating such an environment has never
been gEDA's main focus.  Qucs may be a better tool for that task....

Another point you may be making is that a VHDL like netlist format
could do a better job than gnetlist dealing with this schematic?  But
if you don't include a simulation model for the op-amp and ignore the
syntax required by the tool, then it doesn't matter what your file
format is -- nothing will work properly.

Since you certainly know all of the above, I guess I am a little
confused about your point in making the assertion:

>>  The existing netlister does not work very well.

>From my standpoint, it works quite well within the boundaries for
which is was designed.  If we want a better netlister
(i.e. gnetman++), then that's another matter.

Stuart




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