Re: gEDA-dev: Regarding SoC application

[Lars Johannesen <ljoh06-at-NOSPAMhst_dot_aau_dot_dk>]

>
> The biggest most important need for the simulation part is to 
> redo the translation system according to the VHDL (could be 
> Verilog) proposal I made.  I will be your mentor if you want.  
> This could be a good SoC project, and it will have high 
> visibility.  It takes gEDA into an area where it has not yet 
> been.
>   
Sounds really interesting :) allthough I must admit that I don't know 
much about VHDL, yet - only tried various SPICE programs and Matlab.
> There are texts that would include gEDA and gnucap if we can get 
> this working well enough.
>
> Another place where I need help is with the windows port of 
> gnucap.  This is not a SoC project.  I don't have a Windows 
> system, and with the new use of plugins I don't know what 
> happens on Windows.  I am not likely to do it myself because 
> there is so much other work to do.
>   
Ok, I got a Windows system somewhere - but that part I can look into now 
in my spare time as I haven't found an electronics tool for windows that 
suits all my needs yet.
> There is also the possibility of a version of gnucap without 
> plugins, for windows, if we can't get plugins to work.  I guess 
> that would be like the "crippled demos" you often get in texts.
>
> I think your friends are hurting themselves by learning only 
> windows, but that's their choice.
>   
Can only say that I agree, but the fact is that not everyone uses linux 
many use windows / mac - which is why I figure a windows port could 
prove useful. Maybe just talk with the sysadm. at the department and get 
him to install gEDA on the sunray terminals.
> Back to the translator ...  The biggest problem with the 
> simulation environment has been the incomplete translation from 
> schematic to netlist.  WIth the growth in gnucap capability, 
> there is a growing gap between the capabilities of both gnucap 
> and gschem, and what gets translated.  There is also a need for 
> simulating from layout, from gerber, and other sources, and 
> sharing and relating between them.
>
> Gnucap will be using primarily  VHDL-AMS and Verilog-AMS as 
> input languages, with Spice only for compatibility to read 
> legacy files.  
>
> One benefit of the *AMS languages is that they can be used to 
> express and model just about anything.  This opens up new needs 
> in the schematic and translators, hence the need for the new 
> translators.
>
> So that's my recommendation for a project.  I will come up with 
> details if someone will do the coding.
>   
I will start to work on my application - is there anyway I could contact 
you over irc/icq or something similar to ease the communication?
> Even if SoC doesn't accept, I still need the help.
>   
I'd like to help regardless of the outcome of the SoC application, but 
would like to apply for SoC because it would be nice to combine gpl and 
a job, so I can put more time into it in the summer than otherwise.

Thanks for the input, very appreciated.

Best regards
  Lars



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