gEDA-dev: VHDL Interchange

[Sandy Thom <sandy_dot_thom-at-NOSPAMtiscali_dot_co_dot_uk>]

Al,

I have been intrigued by your suggestions for a VHDL interchange format.
The following is an attempt to convey the idea at a conceptual level for
gschem schematics. I would really appreciate your guidance.

gschem				VHDL
------------------------------------------------------------------------
Design* 	---->		Self contained top level entity with
				a structural architecture describing
				the interconnection of schematics.

Schematic	---->		Entity with ports being electrical 
				connections to other schematics. Version
				number and other top level attributes
				expressed as vhdl attributes. 
				Structural architecture with component
				instantiations and interconnections. 

Components	---->		Entity with ports being the terminals 
				of the device. Attributes expressed as
				vhdl attributes. Behavioural 
				architecture describing component for
				simulation.

Symbols		---->		How to best describe the relationship
				between the component and its symbol? 

Nets		---->		Intuitively I want to describe nets as 
				vhdl signals. It may be necessary to 
				describe a net as a design entity and
				instantiate as a component.
				
* gschem does not yet use the concept of a design but I noticed that
Peter Clifton suggested it in his musings on hierarchy.

Best regards

Sandy Thom



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