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Re: gEDA-dev: New diagram (attempt at UML)
On Thu, 2007-04-05 at 21:05 -0500, John Griessen wrote:
> Hey Mike Jarabek... What about that description of
> your automation methods with makefiles? Weren't you going to tell
> us something about that? Or am I doing some creative remembering?
I may have mentioned it, my apologies if I forgot, but it was basically
trivial. The gnumake makefiles basically looked something like this
(From memory, no guarantee of syntax):
-----
# Makefile for building Netlists from schematics.
VPATH=./sch:./sym
GNETLIST=gnetlist -g verilog
all: toplevel.v block1.v block2.v
toplevel.v: toplevel-1.sch
$(GNETLIST) -o $@ $^
block1.v: block1-1.sch block1-2.sch block1-3.sch
$(GNETLIST) -o $@ $^
block2.v: block2-1.sch block2-2.sch block2-3.sch block2-4.sch
$(GNETLIST) -o $@ $^
# additional dependencies on the symbols -- would be nice to
# automatically generate this part.
toplevel.sch: block1.sym
block1-1.sch block1-2.sch: subblock.sym
#etc..
-----
Having a one to one relationship between a 'schematic' file and the
resulting verilog netlist would be a good thing. As, then the you can
make a simple template rule to process the files, assuming that the
schematics are named toplevel.sch, block1.sch, block2.sch: (Some thought
and careful application of pattern matching might get you there in the
first case too, but it won't be as straightforward as the template
below.)
-----
# Makefile for building Netlists if there is one 'circuit per file'
VPATH=./sch:./sym
%.v: %.sch
gnetlist -g verilog -o $@ %^
all: toplevel.v block1.v block2.v
# additional dependencies on the symbols -- would be nice to
# automatically generate this part.
toplevel.sch: block1.sym
block1.sch: subblock.sym
#etc..
-----
For synthesis we were using a Commercial tool, and in there you added
each of the resulting Verilog files to the project, along with the other
handwritten Verilog files, once the project file was saved, you hit the
big 'Run' button to do the synthesis, or used a command script. Output
netlists were then run through the regular vendor back-end. Simulations
were run similarly, the simulator tool had a project file that was used
to link together the simulation files. Which were not always the exact
same files as for the synthesis. (Things like Memory blocks sometimes
have a behavioural description and a black box description for
synthesis. The black box does not simulate. A 'universal' netlist is
not entirely possible with Verilog 1995.)
--
--------------------------------------------------
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek
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