Re: gEDA-dev: New diagram (attempt at UML)

[Dan McMahill <dan-at-NOSPAMmcmahill_dot_net>]

John Doty wrote:
> 
> On Apr 9, 2007, at 9:03 AM, Peter Clifton wrote:
> 
>> It thus makes (some) sense to have a "circuit" file, which lists the
>> page files making up one circuit. This also makes a good place to put
>> toplevel attributes for this circuit.
> 
> 
> One problem is that when you are netlisting a hierarchy, you need to  
> know when to stop, and that depends on the purpose of the netlist,  not 
> on the design itself. When making a netlist for board layout, the  
> netlister should stop descending when it sees a footprint (so it  
> doesn't try to expand an internal simulation schematic). On the other  
> hand, a model should stop a simulation netlister. Remember that one  
> might, for simulation purposes, model subsystem behavior above the  
> level of parts with footprints. Or in IC design, your parts won't  have 
> footprints. So there isn't necessarily just one list of pages.
> 
> John Doty              Noqsi Aerospace, Ltd.
> jpd@noqsi.com

You are right John.  Hence my earlier email describing the cadence 
switch list/stop list approach for netlisting along with the hierarchy 
editor they have.  I can't recall if I explicitly stated it in my other 
email, but with the hierarchy editor, you can have multiple 
configurations for a given top level cell.  Each configuration specifies 
the views to use for different cells.  It also has capabilities to 
specifie the views and an inherited switch/stop view list for cells and 
instances.  It is really quite powerful and works fairly well.  It is 
one aspect of cadence that I don't really have complaints about.


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