Re: gEDA-dev: New diagram (attempt at UML)

["Svenn Are Bjerkem" <svenn-at-NOSPAMbjerkem_dot_de>]

On 4/10/07, John Doty <jpd@wispertel.net> wrote:
>
> On Apr 9, 2007, at 10:38 PM, Steve Meier wrote:
>
> > I stop my netlister when a symbol has no associated shematic.
> > source=next.sch I think is the attribute.
>
> Yes, but that isn't always what is needed. For IC design, I generally
> want to preserve the hierarchy, so I do *not* want the netlister to
> follow the "source=" attribute, but rather include the subcircuit
> netlist. Right now, this means I can't use source= in an IC
> schematic, which is a modest inconvenience when using gschem.

Has anybody managed to use gschem to handle an IC design? How?

>
> For PC design, if there's a footprint= attribute, that's the place to
> stop, because if there's also a source= attribute it represents a
> circuit that's there for simulation purposes. But if you're doing
> simulation...
>

Why not "borrow" from Cadence and use the concept of views? Define a
view class for each type of view and let the user assign it a name at
his discretion. Example from Cadence is that a schematic is a view of
class schematic even if it is called schematic_v1p1. A layout is a
layout even if it is called layout_v1p1 etc. You would then need to
create a hierarchy manager (Like Cadence also had to do when stop
lists were not enough) but you would, of course, not make the same
mistakes with that manager like Cadence did.

For those who don't know what Cadence is doing: Each graphical work,
symbol, schematic, layout, extracted view, etc. is recognized by the
software by its class and not by the name.   This give the designers a
freedom to have many views for the same cell. (This is not always
good, but with revision management it has its advantages). When
creating a netlist for the entire design, the hierarchy editor is
launched to pre-select which view is used for which cell. These
configs are also views and can have any name, i.e. you can save a
config for pre-layout, post-layout, concept (with AMS-views) etc. Very
nice when you want to do a concept sim with abstract verilog models
you select the abstract-config, and when you want to perform an
extracted view simulation you select the av_extracted view for the
netlister.

This is how Cadence does it. I don't think this is the best solution,
but it must work for most IC designers out there. (If you look at the
market share of cadence tools)

You could look at the need that is in a hierarchy editor like a make
with certain pre-selection possibilities. (My preferred way would be
to have a graphical tool for configuration and then be able to fire
off a command line tool taking that config view as an option to create
a new netlist.)
-- 
Svenn


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