Re: gEDA-dev: New diagram (attempt at UML)

[Steve Meier <smeier-at-NOSPAMalchemyresearch_dot_com>]

John,

The PCB and pads netlist formats are flat formats. Is these a netlist
format that you would recommend that is hierarchical?

Steve Meier

On Tue, 2007-04-10 at 13:23 -0700, Steve Meier wrote:
> I don't follow you here.
> 
> I understand that you want to keep the hierarchy. So do I. Following the
> source= attribute just tells me which schematics are needed.
> 
> 
> Pass 1) Create list of unique files. This is the first time I follow the
> branches of the hierarchical tree
> 
> 
> Pass 2) Collect components, nets and buses for each unique file
> 
> This creates netlists and buslists for each schematic page.
> 
> 
> Pass 3) Flatten pages to make a super page that has all instances of
> all components, nets and buses. This is the second time I follow the
> branches of the hierarchical tree. Hierarchical Information is retained.
> net names are hierarchicaly adjusted. Buses are converted to nets.
> 
> When I flaten the net I still retain the hierarchy information. Also, I
> use the step 2 nets and buses repeatedly adjusting the hierarchy as they
> are added to the overall design
> 
> 
> Warning: My version is not the standard geda distribution.
> 
> Steve Meier
> 
> 
> On Tue, 2007-04-10 at 08:51 -0600, John Doty wrote:
> > On Apr 9, 2007, at 10:38 PM, Steve Meier wrote:
> > 
> > > I stop my netlister when a symbol has no associated shematic.
> > > source=next.sch I think is the attribute.
> > 
> > Yes, but that isn't always what is needed. For IC design, I generally  
> > want to preserve the hierarchy, so I do *not* want the netlister to  
> > follow the "source=" attribute, but rather include the subcircuit  
> > netlist. Right now, this means I can't use source= in an IC  
> > schematic, which is a modest inconvenience when using gschem.
> > 
> > For PC design, if there's a footprint= attribute, that's the place to  
> > stop, because if there's also a source= attribute it represents a  
> > circuit that's there for simulation purposes. But if you're doing  
> > simulation...
> > 
> > >
> > > Steve Meier
> > >
> > > John Doty wrote:
> > >>
> > >> On Apr 9, 2007, at 9:03 AM, Peter Clifton wrote:
> > >>
> > >>> It thus makes (some) sense to have a "circuit" file, which lists the
> > >>> page files making up one circuit. This also makes a good place to  
> > >>> put
> > >>> toplevel attributes for this circuit.
> > >>
> > >> One problem is that when you are netlisting a hierarchy, you need to
> > >> know when to stop, and that depends on the purpose of the netlist,  
> > >> not
> > >> on the design itself. When making a netlist for board layout, the
> > >> netlister should stop descending when it sees a footprint (so it
> > >> doesn't try to expand an internal simulation schematic). On the other
> > >> hand, a model should stop a simulation netlister. Remember that one
> > >> might, for simulation purposes, model subsystem behavior above the
> > >> level of parts with footprints. Or in IC design, your parts won't  
> > >> have
> > >> footprints. So there isn't necessarily just one list of pages.
> > >>
> > >> John Doty              Noqsi Aerospace, Ltd.
> > >> jpd@noqsi.com
> > >>
> > >>
> > >>
> > >>
> > >> _______________________________________________
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> > >> geda-dev@moria.seul.org
> > >> http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
> > >>
> > >
> > >
> > >
> > > _______________________________________________
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> > 
> > John Doty              Noqsi Aerospace, Ltd.
> > jpd@noqsi.com
> > 
> > 
> > 
> > 
> > _______________________________________________
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> > geda-dev@moria.seul.org
> > http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
> 
> 
> 
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