Re: gEDA-dev: New diagram (attempt at UML)

[John Doty <jpd-at-NOSPAMwispertel_dot_net>]

On Apr 10, 2007, at 6:28 PM, al davis wrote:

>
>> On Apr 10, 2007, at 2:36 PM, Steve Meier wrote:
>>> The PCB and pads netlist formats are flat formats. Is these
>>> a netlist format that you would recommend that is
>>> hierarchical?
>>
>>> On Tuesday 10 April 2007 17:13, John Doty wrote:
>> SPICE.
>
> If the year is 1975, I would agree with you.
>
> If the year is 1990, I would accept that as an
> ultra-conservative statement.  Those in the know were already
> pushing to move on.
>
> For today: Verilog-AMS or VHDL-AMS.

When my customers want that, I'll go that way. I might look into it,  
and nudge them a little. You have me interested. But on my last (and  
first) IC design, the deliverable in the contract was a SPICE netlist.

In any case, can't these new formats handle hierarchy? I would think  
it preferable to let the simulator do the expansion, not the  
netlister. Am I missing something?

John Doty              Noqsi Aerospace, Ltd.
jpd@noqsi.com




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