Re: gEDA-dev: New diagram (attempt at UML)

[al davis <ad136-at-NOSPAMfreeelectron_dot_net>]

On Tuesday 10 April 2007 20:59, John Doty wrote:
> In any case, can't these new formats handle hierarchy? I
> would think   it preferable to let the simulator do the
> expansion, not the netlister. Am I missing something?

Of course they can.  The question at the top was
>>> Is these
>>> a netlist format that you would recommend that is
>>> hierarchical?

On Tuesday 10 April 2007 20:59, John Doty wrote:
> When my customers want that, I'll go that way. I might look
> into it,   and nudge them a little. You have me interested.
> But on my last (and first) IC design, the deliverable in the
> contract was a SPICE netlist.

We need to design for the future.  We have a Spice netlister 
that works as well as can be expected for a Spice netlister.  
The Verilog netlister does not support attributes, or any of 
the analog extensions.

What Spice do they want?  HSpice?  PSpice? NG-spice?

I don't know what the priorities of the other developers are, 
but for me the people doing free/open-source hardware 
development are the top priority.  We are the enabler for that, 
in the same sense that gcc was the enabler for the whole 
free/open-source software movement.  Another priority for me is 
a base for researchers, so they can build on free tools rather 
than proprietary ones.

If there is are commercial users, that's fine, but not the 
highest priority.  If some of them want to send some money this 
way, they could move to the top.

The highest interest in gnucap is absolutely in the promise of a 
fast, free (GPL) Verilog-AMS simulator.  They would like other 
tools (schematic, layout, timing analysis, ...) that work with 
it too.

The interest I have gotten from the gEDA community is small by 
comparison.


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