Re: gEDA-dev: New diagram (attempt at UML)

[Dan McMahill <dan-at-NOSPAMmcmahill_dot_net>]

John Doty wrote:
> 
> On Apr 10, 2007, at 3:26 PM, Steve Meier wrote:



> I think so. You don't want to try to lay out the innards of an IC on  a 
> PC board.
> 
>> I should then also mark if
>> the page has a physical realization (for PCB) or not (for simulation).
> 
> 
> I think if it has a footprint, that's evidence that this is the level  
> that goes on a PC board. If it has a model, that's evidence that this  
> is the level where you use the model rather than the source for  
> simulation (if you have no model and no source, the symbol should  
> represent a simulation primitive like a resistor). But Svenn seems to  
> have more ambitious ideas: you might want to understand how Cadence  
> does it (don't ask me!).

I think the cadence model works well.  It is not too complicated 
(really) and provides a tremendous amount of flexibility and I think 
addresses all of the needs I've heard here.

>>
>> By the way, it has been my intention to make the third step ("flatten
>> nets") a function that is called from schem.
> 
> 
> Why? Let gschem's focus stay on graphical entry. Use a separate  utility 
> for netlisting. Very flexible and scriptable. "A program  should do one 
> thing well".
> 
>>
>> OK i will take a look at the spice netlist format and start working on
>> getting that working.

I think that may be premature. First a solid framework for walking 
through a hierarchy and producing a hierarchical netlist (of any format) 
needs to be in place.  Then spice, verilog, vhdl, whatever should be 
fairly easy.




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