Re: gEDA-dev: New diagram (attempt at UML)

[Dan McMahill <dan-at-NOSPAMmcmahill_dot_net>]

John Doty wrote:

>> The highest interest in gnucap is absolutely in the promise of a
>> fast, free (GPL) Verilog-AMS simulator.  They would like other
>> tools (schematic, layout, timing analysis, ...) that work with
>> it too.
> 
> 
> I have no axe to grind here, but I've little clue as to what Verilog- 
> AMS is and what it can do. Since vendors provide SPICE models, it's  
> hard to understand how I could actually use it.
> 

among other things, you can generate a complex behavioural model for 
certain of your circuit blocks.  This can help in terms of verifying 
your larger system as well as speeding up simulations.  Suppose you have 
a cell that has several subcells inside it that all must be present to 
really simulate what you need.  But perhaps you don't need transistor 
level accuracy on all of the blocks.  Write verilog-ams models for them.

Of course this gets back to the need for some real control over the 
netlister in a way which is not intrusive into the schematics for the 
design.

-Dan


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