Re: gEDA-user: What's your way of syncing CPLD design and gschemsymbols???

[Christoph Lechner <cl0023-atMUNGEDl-mx_dot_de>]

Andy Peters schrieb:
> 
> It might be easier to work backwards, from the schematic, and have it 
> back-annotate into the .ucf (user constraint file), which is the file 
> used by the Xilinx tools for pinouts (and timing specs, etc etc).  It 
> gets even more complicated when schematic net names don't match the CPLD 
> design pin names, or when you connect the same schematic net to two FPGA 
> pins (like when doing external clock feedback).
> 
> This isn't really a problem for small CPLDs but it's a right royal PITA 
> with large FPGAs.
Fortunately I only use XC9572XL CPLDs for most of
my designs :)

And as you already wrote there's no problem with the
net names, as they map 1:1 between the VHDL source
and the schematic symbol.

- cl


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