Re: gEDA-user: What's your way of syncing CPLD design and gschemsymbols???

[Dave McGuire <mcguire-atMUNGEDneurotica_dot_com>]

On Mar 8, 2007, at 5:20 PM, Andy Peters wrote:
>> The timing issues following from forcing the Xilinx tool
>> to use a user-defined pin-out are non-trivial IMHO, at
>> least for CPLDs. So I guess it would be better regarding
>> timing issues to run Xilinx ISE (or another vendor's tool)
>> first and then go to gschem and create/update the symbol.
>
> For older architectures, it was definitely a requirement that you  
> let the tools assign the pins.  But in my recent designs, using  
> CoolRunner CPLDs and Spartan IIE and 3E and Acex FPGAs, I assign  
> pins as needed by the layout, and I've never had problems meeting  
> timing, nor have I had fitting issues.
>
> The XC3000 and 95xx parts are dead!

   Really?  That's interesting.  My XC9500s are working just fine.

          -Dave

-- 
Dave McGuire
Port Charlotte, FL




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