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Re: gEDA-user: simulation advice

On 4/3/07, al davis <ad136@freeelectron.net> wrote:
> One more point ...
>
> Node names are case sensitive.
>
> I suppose I should change it, but that part of the code is
> planned for major rework anyway, and Verilog is supposed to be
> case sensitive.

I'm a 20 year Unix veteran.  I prefer case sensitivity :-)

--wpd


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