Re: gEDA-user: Re: iverilog: Parameters of Parameters

[Evan Lavelle <sa212+geda-atMUNGEDcyconix_dot_com>]

lingwitt@bellsouth.net wrote:

> However, the lack of such a feature shows
> the poor thought of Verilog's designers.

Sssh.... they're out there somewhere, and they may be listening.


> The burden is on the programmer, not
> the tools.

The main problem with both Verilog and VHDL is that they're both 
early-80's languages, and there just aren't enough potential users to 
ensure that the academics get interested enough to fix things. Pretty 
much everything is vendor-driven in EDA, which leads inevitably to 
absurdities like SystemVerilog.

Of Verilog and VHDL, one was an interesting amateur experiment, which 
should have been quietly killed off after a year or two. The other was 
actually pretty good for its time, but was too complex for its target 
audience.


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