Re: gEDA-user: Anyone have any success with Icarus Verilog and Altera's Quartus software?

[Charles Lepple <clepple-at-NOSPAMghz_dot_cc>]

On Saturday, May 3, 2003, at 11:47  AM, Stephen Williams wrote:

> clepple@ghz.cc said:
>> I'm evaluating Altera's Quartus II software (roughly same capabilities
>>  as Xilinx's Webpack) and I was wondering if anyone had done any
>> successful P+R in Quartus with the EDIF output of Icarus Verilog.
>
> The tgt-edif module is very old. It likely won't work.

not terribly surprising.

On the other hand, it does have some handy-looking Verilog modules that 
the author used to deduce the proper architecture-specific dialect of 
EDIF.

> The tgt-fpga module now bundled and under development works much
> better, but would need some code added to support your target device.
> You need to add a part "architecture", which I'm trying to make as
> easy to do as possible. See for example the virtex2 support.

OK. I'll look at that on Monday, as I will need to figure out what the 
Altera EDIF parser wants for all of the basic cells.

> Since the past few years, you're the first person to ask about
> Altera support:-)

Well, it's a toss-up between Xilinx and Altera at work, but Altera does 
seem to have viable, well-priced alternatives to the Spartan II/IIE. 
Plus, I seem to remember something about 5V-tolerant I/O pins, although 
that may have been a different family.

-- 
Charles Lepple <clepple@ghz.cc>
http://www.ghz.cc/charles/