Re: GPLd PCB Library ( was Re: gEDA-user: Free GNU/Linux hardwaredesign tools)

[Stephen Meier <smeier-at-NOSPAMAlchemyResearch_dot_com>]

John Dalton wrote:

>>Once in the open source domain it becomes the responsibility of it's 
>>users to enhance, maintain and document. With that in mind I am 
>>releasing a paper on Land Pattern Design for PCB.
>>    
>>
>
>This is probably the time to mention that I am writing a GPLd
>PCB library generator.  It implements all of IPC-SM-782A.
>
>Just for the fun of it, I decided to write it in terms
>of 3D modeling.  That lets it do nifty things like:
>- If your package is non-standard, put in its dimensions and
>  the library widget will generate a SMT land pattern for it, based
>  on the rules in IPC-SM-782A.
>- It is able to generate a 3D (VRML) representation of the package
>  and its lands.
>
>It is planned to be a stand alone module, with some sort of a standard
>interface (SOAP or similar?).  Input will be either a package
>designation or package dimensions.  Output will be VRML representing
>the package and its lands.  Filters will be used to convert the VRML
>into the desired format.
>
>Given the nature of the interfaces, it should be possible to set
>the library up as a networked server, serving land patterns and
>so on to EDA tools.  Alternatively, it can be run as a stand alone
>command line program, possibly with a graphical front end, and
>used to generate a PCB library in your favourite format.   Yet again,
>it should be possible to write a 'compatibility layer' and integrate
>it directly into an EDA tool.
>
>So far, I have entered and verified all the required data from
>IPC-SM-782A.  I have also written a set of classes which can represent
>at least some of the available packages.
>
>Work is continuing on expanding the set of classes until they can
>represent every package in the standard.  Work has also started on
>the classes which generate a land pattern, given the package
>representation.
>
>In the last month or so development has come to a halt due
>to other commitments, but I hope to have another burst of activity
>soon and get it finished and released.
>
>As a taster, some of the output from what I have written so far
>is appended to this email.  Cut and past the VRML to a file and
>view it with something like 'freewrl'
>
>Best wishes
>John
>
>  
>
John,

I would happily give you a hand at this but I caution. Each land pattern 
must match the manufacturing and assembly method. I was discussing thess 
issues this morning with a flex circuit company and their recomended 
assembly partner. On the other hand, they seem happy to take what we 
produce as gerber files and modify them (shape of pads, amount that 
solder mask covers component area, gang versus individual solder masks, 
shape of vias, etc.) Back to the caution. One manufacturing process 
might not match a second. For pcbs the requirements will be different 
then flex circuits. All this has had me scratching my head since I have 
to design, layout and get manufactured boards (can a flex circuit be 
caled a board?) . The abstraction will be challenging.

Just as an aside, todays horror is that I am trying to put a flip chip 
on a ridged-flex board with 45 contacts at a worse case pitch of 8 mils. 
the assembly and flex circuit company didn't even flinch. Yes I am doing 
all this with geda tools and pcb. Also the vhdl emulator Icarus is 
usable and has allowed me to emulate designs that I have then used free 
(as in beer) Altera tools to program altera chips (limited down rev 
chips being supported in the "free" version.)


Cheers,

Steve M.