cfk wrote: > I understand that the 8 bits of i can grow to 9 bits with a > carryout when i is maxed out. So, 8 + 9 > 16 and thats a problem. I don't think you will get the 9th bit. I don't think verilog will automagically resize your vector from 8 to 9 bits. Not a verilog expert, Gus