Icarus Verilog
GPLed Verilog Compilation System
What is Icarus Verilog?
Icarus Verilog is a a GPLed Verilog compiler. Icarus Verilog includes a
a parser that parses Verilog (plus extensions) and generates an
internal netlist. The netlist is passed to various processing steps
that transform the design to more optimal/practical forms, then passed
to a code generator for final output. The processing steps and the code
generator are selected by command line switches.
For the latest test plan please go to ftp://icarus.com/pub/eda/verilog/tests
Please send all comments/suggestions directly to Stephen Williams
(e-mail is listed below.)
What are the latest features in the current release?
Please go to
http://icarus.com/eda/verilog/index.html for the latest info.
What does it look like?
There are no screenshots at this point. Icarus Verilog is a text/command
line program.
Who is the author of Icarus Verilog?
Stephen Williams
steveATicarus.com
Official website of Icarus Verilog is:
http://www.icarus.com/eda/verilog/
What is the current version?
20070227 (snapshot) and v0.8.3 (stable)
Where can I download it?
gEDA's download page
Binaries:
Icarus Verilog ftp
Official
Icarus Verilog homepage
